Semester
Spring
Date of Graduation
2008
Document Type
Thesis
Degree Type
MS
College
Statler College of Engineering and Mineral Resources
Department
Lane Department of Computer Science and Electrical Engineering
Committee Chair
Afzel Noore.
Abstract
This thesis addresses the problem of implementing reliable FPGA-based shifters. An FPGA-based design requires optimization between performance and resource utilization, and an effective verification methodology to validate design behavior. The FPGA-based implementation of a large shifter design is restricted by an I/O resource bottleneck. The verification of the design behavior presents a further challenge due to the 'black-box' nature of FPGAs. To tackle these design challenges, we propose a novel approach to implement FPGA-based shifters. The proposed design alleviates the I/O bottleneck while significantly reducing the logic resources required. This is achieved with a minimal increase in the design delay. The design is seamlessly scalable to a multi-FPGA chip setup to improve performance or to implement larger shifters. It is configured using assertion checkers for efficient design verification. The assertion-based design is further optimized to alleviate the performance degradation caused by the assertion checkers.
Recommended Citation
Syed, Zahid Ali, "Performance and area optimization for reliable FPGA-based shifter design" (2008). Graduate Theses, Dissertations, and Problem Reports. 1963.
https://researchrepository.wvu.edu/etd/1963