Date of Graduation


Document Type

Problem/Project Report

Degree Type



Statler College of Engineering and Mineral Resources


Lane Department of Computer Science and Electrical Engineering

Committee Chair

David Graham

Committee Member

Roy Nutter

Committee Member

Jeremy Dawson


Two low-power voltage reference cells for a system on-chip design are presented in this report. Both cells utilize a combination of standard transistors to produce an output voltage near 1 volt. Choosing the appropriate design procedures can aid in minimizing the temperature coefficient (TC) of the output reference voltage coming out of the cell. One circuit, covered first, is currently being fabricated on a standard 0.5 µm chip complementary metal oxide semiconductor (CMOS) process, while the other is still in the designing stage. The first one has a TC of 86 ppm/◦C with a reference voltage of 1.10 V while consuming 1.25 µW of power by simulation. The second voltage reference cell is aimed for a lower TC, and power consumption approximately 37 ppm/◦C and 2 nW in simulation. Additionally, ideas to improve the circuits will be explored, and the layout of the first cell will be presented in this paper.