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Advanced packaging and high density interconnections are emerging technologies as silicon MOS device dimensions scale down to minimum physical limits. Multi-chip Modules and Wafer Scale Integration improve packing density, and provide solutions to board area issues beyond the capabilities of even the most densely packed surface mount technologies. Such technologies could confront increasingly complex interconnection constraints, and might provide opportunities for the insertion of high performance optical interconnections into future microelectronic systems. However, successful integration of optics with microelectronic system technologies requires a careful evaluation of the practical issues confronting monolithic co-integration of GaAs optoelectronics with high performance silicon CMOS technologies. This work presents a systematic evaluation of degradation in the performance and characteristics of submicron silicon CMOS devices, induced by heteroepitaxial growth of gallium arsenide. An aggressive yet stable, commercial 0.9 {dollar}\\mu{dollar}m AT&T Twin-Tub V silicon CMOS fabrication process is used to study the compatibility issues.