Date of Graduation


Document Type


Degree Type



Statler College of Engineering and Mineral Resources


Lane Department of Computer Science and Electrical Engineering

Committee Chair

Powsiri Klinkhachorn.


The objective of this thesis is to design and implement an FPGA-based softcore processor with hardware Real Time Operating System (RTOS).;RTOSs provide an abstracted environment on top of the hardware with different mechanisms to simplify and coordinate the behavior of the system. Software mechanisms including multithreading, semaphores, timers, interrupts, etc. consume large amounts of CPU time which increases overhead and contributes to the degradation of the performance. In order to offload this overhead, RTOSs with hardware acceleration have been a research topic with considerable interest. Most research works are focused on the design of a hardware RTOS external to the CPU where CPU interacts with the hardware RTOS module as a memory mapped device. This approach provides the flexibility of using the general purpose processor, however, fast context switching is not possible unless a special CPU with a duplicated register file is equipped. To this end, tightly coupling the RTOS functionality to the CPU pipeline is a good candidate for further investigation. Multithreaded processors are a distinct area of research focusing on reducing the pipeline hazards by interleaving instructions from different threads. Most of the multithreading techniques support fast context switching mechanisms in order to support cycle interleaving of instructions. The fast context switching ability inherent to multithreaded processors can be used to implement OS level multithreading and low latency interrupt service threads. This thesis investigates on the possibilities of merging previous research work on hardware RTOSs and multithreaded processors to obtain an overall improvement. Attachment of a hardware RTOS to the pipeline increases the determinism by eliminating external interfaces with nondeterministic bus arbitration schemes and reduces the logic required to implement the external interfaces.;The implemented prototype processor is instruction set compatible with Xilinx Microblaze and has a five stage multithreaded pipeline. The pipeline is extended with a static priority preemptive scheduler, semaphore and timer modules. The instruction set is augmented with several instructions to support thread creation, deletion, synchronization and time management. Results suggest that RTBlaze can completely remove the OS overhead at the cost of doubled processor size. Zero overhead scheduler, context switching, thread synchronization, timers and five-cycle interrupt latency give excellent performance as well as the increased determinism compared with software RTOSs.