Semester
Summer
Date of Graduation
2006
Document Type
Thesis
Degree Type
MS
College
Statler College of Engineering and Mineral Resources
Department
Industrial and Managements Systems Engineering
Committee Chair
B Gopalakrishnan
Abstract
The CMOS microchip is the workhorse of the semiconductor industry. An estimated price of a CMOS chip for an 8" wafer was stated as {dollar}1.65/chip (65). The manufacturing model was formed with practical processing times, number of machines, steps of manufacturing process, labor required, construction costs, land costs, etc as input parameters. This cost model attempts to analyze costs and calculate the cost per chip. Different sections of costs have been individually analyzed in turn to reflect their impact on the finished product. A simulation model has been run to reflect an actual semiconductor manufacturing scenario. Simulation model is also used to estimate labor required for the process.;The cost was calculated based on yield, number of chips/wafer and total expenditure by the fab. A simulation model was created in Arena 6.0 professional version, which allows the user to make changes to the model to reflect the changes in the fab. The calculated cost of the model for a CMOS chip was obtained as {dollar}0.75/chip.
Recommended Citation
Gajera, Dipesh, "Process costing of microchip" (2006). Graduate Theses, Dissertations, and Problem Reports. 4228.
https://researchrepository.wvu.edu/etd/4228